Altera Cyclone V Device Handbook page 241

7-26
JTAG Single-Device Configuration
Figure 7-17: JTAG Configuration of a Single Device Using a Download Cable
If you only use the JTAG configuration, connect
nCONFIG to V
Pull DCLK either high or low whichever is
convenient on your board. If you are using JTAG
in conjunction with another configuration scheme,
connect MSEL[4..0], nCONFIG, and DCLK based
on the selected configuration scheme.
To configure a Cyclone V device using a microprocessor, connect the device as shown in the following figure.
You can use JRunner as your software driver.
Figure 7-18: JTAG Configuration of a Single Device Using a Microprocessor
ADDR
Microprocessor
Related Information
AN 414: The JRunner Software Driver: An Embedded Solution for PLD JTAG Configuration
Altera Corporation
V V
CCPGM CCPGM
FPGA Device
10 kΩ 10 kΩ
nCE
N.C. nCEO
GND
nSTATUS
CONF_DONE
nCONFIG
MSEL[4..0]
DCLK
and MSEL[4..0] to GND.
CCPGM
Memory
DATA
Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
V
CCPD
V
CCPD
TCK
TDO
TMS
TDI
Pin 1
1 kΩ
GND
Connect the pull-up resistor to a supply that
provides an acceptable input signal for all
FPGA devices in the chain. V
high enough to meet the V
the I/O on the device.
10 kΩ
FPGA Device
nSTATUS
CONF_DONE
TDI
DCLK
TCK
nCONFIG
TMS
MSEL[4..0]
TDO
nCEO N.C.
nCE
GND
The microprocessor must use
the same I/O standard as
V to drive the JTAG pins.
CCPD
The resistor value can vary
from 1 kΩ to 10 kΩ. Perform
signal integrity analysis to
select the resistor value for
your setup.
Connect the pull-up
resistor V .
CCPD
Download Cable
10-Pin Male Header
(JTAG Mode) (Top View)
V
CCPD
GND
GND
must be
CCPGM
specification of
IH
V V
CCPGM CCPGM
10 kΩ
If you only use the JTAG configuration,
connect nCONFIG to V and
CCPGM
MSEL[4..0] to GND. Pull DCLK high or
low. If you are using JTAG in conjunction
with another configuration scheme, set
the MSEL[4..0] pins and tie nCONFIG and
DCLK based on the selected
configuration scheme.
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CV-52007
2014.01.10