Write Combining; Burst Length Support; Ecc - Altera Cyclone V Device Handbook

8-10

Write Combining

If the controller determines that the next pending command will cause the bank request to not be honored,
the bank might be held open or closed depending on the pending operation. A request to close a bank with
a pending operation in the timer bank pool to the same row address causes the bank to remain open. A
request to leave a bank open with a pending command to the same bank but a different row address causes
a precharge operation to occur.
Write Combining
The SDRAM controller combines write operations from successive bursts on a port where the starting address
of the second burst is one greater than the ending address of the first burst and the resulting burst length
does not overflow the 11-bit burst-length counters.
Write combining does not occur if the previous bus command has finished execution before the new command
has been received.

Burst Length Support

The controller supports burst lengths of 2, 4, 8, and 16, and data widths of 8, 16, and 32 bits for non-ECC
operation, and widths of 24 and 40 operations with ECC enabled. The following table shows the type of
SDRAM for each burst length.
Table 8-3: SDRAM Burst Lengths
Burst Length
Width Matching
The SDRAM controller automatically performs data width conversion.

ECC

The single-port controller supports memory ECC calculated by the controller. The controller ECC employs
standard Hamming logic to detect and correct single-bit errors and detect double-bit errors. The controller
ECC is available for 16-bit and 32-bit widths, each requiring an additional 8 bits of memory, resulting in an
actual memory width of 24-bits and 40-bits, respectively.
Altera Corporation
4
8
16
SDRAM
LPDDR2, DDR2
DDR2, DDR3, LPDDR2
LPDDR2
SDRAM Controller Subsystem
cv_54008
2013.12.30
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