Altera Cyclone V Device Handbook page 957

20-6
Transmitting and Receiving Protocol
Figure 20-5: 10 - Bit Address Format
The following table defines the special purpose and reserved first byte addresses. †
Table 20-1: I2C Definition of Bits in First Byte †
Slave Address
0000 000
0000 000
0000 001
0000 010
0000 011
0000 1XX
1111 1XX
1111 0XX
Note to Table:
1. 'X' indicates do not care.
Related Information
START BYTE Transfer Protocol
Transmitting and Receiving Protocol
The master can initiate data transmission and reception to or from the bus, acting as either a master-
transmitter or master-receiver. A slave responds to requests from the master to either transmit data or receive
data to or from the bus, acting as either a slave-transmitter or slave-receiver, respectively. †
Master-Transmitter and Slave-Receiver
All data is transmitted in byte format, with no limit on the number of bytes transferred per data transfer.
After the master sends the address and R/W bit or the master transmits a byte of data to the slave, the slave-
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S 1 1 1 1 0 A9
Reserved for 10-Bit Address
S: Start Condition
R/W: Read/Write Pulse
ACK: Acknowledge (Sent by Slave)
0
1
X
X
X
X
X
X
on page 20-8
A8 R/W ACK A7 A6 A5 A4 A3
R/W Bit
A2 A1 A0 ACK
Description
General call address. The I2C
controller places the data in the
receive buffer and issues a general
call interrupt.
START byte. For more details,
refer to "START BYTE Transfer
Protocol"
CBUS address. The I2C controller
ignores these accesses.
Reserved
Reserved
Unused
Reserved
10-bit slave addressing.
I2C Controller
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2013.12.30