Transmitter Pcs Datapath - Altera Cyclone V Device Handbook

1-28

Transmitter PCS Datapath

Transmitter PCS Datapath
Table 1-11: Blocks in the Transmitter PCS Datapath
Block
Transmitter Phase Compensation
FIFO
Byte Serializer
8B/10B Encoder
Transmitter Bit-Slip
Transmitter Phase Compensation FIFO
The transmitter phase compensation FIFO is four words deep and interfaces with the transmitter channel
PCS and the FPGA fabric or PCIe hard IP block. The transmitter phase compensation FIFO compensates
for the phase difference between the low-speed parallel clock and the FPGA fabric interface clock.
Figure 1-22: Transmitter Phase Compensation FIFO
The transmitter phase compensation FIFO supports two operations:
• Phase compensation mode with various clocking modes on the read clock and write clock
• Registered mode with only one clock cycle of datapath latency
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• Compensates for the phase difference between the low-speed parallel
clock and the FPGA fabric interface clock, when interfacing the
transmitter PCS with the FPGA fabric directly or with the PCIe hard
IP block
• Supports operation in phase compensation and registered modes
• Halves the FPGA fabric transceiver interface frequency at the
transmitter channel by doubling the transmitter input datapath
width
• Allows the transmitter channel to operate at higher data rates with
the FPGA fabric transceiver interface frequency that is within the
maximum limit
• Supports operation in single- and double-width modes
• Generates 10-bit code groups from 8-bit data and the 1-bit control
identifier in compliance with Clause 36 of the IEEE 802.3 specifica-
tion
• Supports operation in single- and double-width modes and running
disparity control
• Enables user-controlled, bit-level delay in the data prior to
serialization for serial transmission
• Supports operation in single- and double-width modes
Compensation
Datapath from the FPGA
Fabric or PIPE Interface
wr_clk
tx_coreclk
Functionality
TX
Phase
Datapath to the Byte Serializer
FIFO
or the 8B/10B Encoder or Serializer
rd_clk
tx_clkout
coreclkout
Transceiver Architecture in Cyclone V Devices
CV-53001
2013.05.06
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