Altera Cyclone V Device Handbook page 724

11-46
Internal DMA Controller Transmission Sequences
• If the internal DMA controller enable bit (de) of the bmod register is set to 0 during the middle of a
DMA transfer, the change has no effect. Disabling only takes effect for a new data transfer command.
• Issuing a software reset immediately terminates the transfer. Prior to issuing a software reset, Altera
recommends the host reset the DMA interface by setting the dma_reset bit of the ctrl register
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to 1.
• The pbl field of the bmod register is read-only and a direct reflection of the contents of the DMA
multiple transaction size field (dw_dma_multiple_transaction_size) in the fifoth
register.
• The fb bit of the bmod register has to be set appropriately for system performance.
2. Write to the idinten register to mask unnecessary interrupt causes according to the following
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guidelines:
• When a Descriptor Unavailable interrupt is asserted, the software needs to form the descriptor,
appropriately set its own bit, and then write to the poll demand register (pldmnd) for the internal
DMA controller to re-fetch the descriptor.
• It is always appropriate for the software to enable abnormal interrupts because any errors related to
the transfer are reported to the software.
3. Populate either a transmit or receive descriptor list in memory. Then write the base address of the first
descriptor in the list to the internal DMA controller's descriptor list base address register (dbaddr). The
DMA controller then proceeds to load the descriptor list from memory. Internal DMA Controller
Transmission Sequences and Internal DMA Controller Reception Sequences describe this step in detail.
Related Information
• Internal DMA Controller Transmission Sequences
Refer to this section for information about the Internal DMA Controller Transmission Sequences.
• Internal DMA Controller Reception Sequences
Refer to this section for information about the Internal DMA Controller Reception Sequences.
Internal DMA Controller Transmission Sequences
To use the internal DMA controller to transmit data, perform the following steps:
1. The host sets up the Descriptor fields (DES0 DES3) for transmission and sets the OWN bit (DES0[31])
to 1. The host also loads the data buffer in system memory with the data to be written to the SD card.
2. The host writes the appropriate write data command (SD/SDIO WRITE_BLOCK or
WRITE_MULTIPLE_BLOCK) to the cmd register. The internal DMA controller determines that a write
data transfer needs to be performed.
3. The host sets the required transmit threshold level in the tx_wmark field in the fifoth register.
4. The internal DMA controller engine fetches the descriptor and checks the OWN bit. If the OWN bit is
set to 0, the host owns the descriptor. In this case, the internal DMA controller enters the suspend state
and asserts the Descriptor Unable interrupt. The host then needs to set the descriptor OWN bit to 1 and
release the DMA controller by writing any value to the pldmnd register.
5. The host must write the descriptor base address to the dbaddr register.
6. The internal DMA controller waits for the Command Done (CD) bit in the rintsts register to be set
to 1, with no errors from the BIU. This condition indicates that a transfer can be done.
7. The internal DMA controller engine waits for a DMA interface request from BIU. The BIU divides each
transfer into smaller chunks. Each chunk is an internal request to the DMA. This request is generated
based on the transmit threshold value.
Altera Corporation
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on page 11-46
on page 11-47
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SD/MMC Controller
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2013.12.30
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