Altera Cyclone V Device Handbook page 804

16-8
How to Set the Security State for the Interrupt Outputs
Note:
When set, the security state remains constant until a state transition on the dma_rst_n signal resets
the DMAC.
Related Information
• DMA Manager Thread in Secure State
Describes how the security state of the DMA manager affects how the DMAC operates.
• DMA Manager Thread in Non-Secure State
How to Set the Security State for the Interrupt Outputs
The DMAC provides the boot_irq_ns[7:0] signals to enable you to assign each irq[x] signal to a
security state.
The boot_irq_ns[7:0] signals connect to the system manager. Before taking the DMA out of reset,
you should program boot_irq_ns[7:0] through the system manager to control which interrupt bits
are secure.
Note: The DMAC samples the boot_irq_ns[7:0] bits immediately after it comes out of reset, and
then ignores them until the next reset.
When set, the security state of each irq[x] signal remains constant until a state transition on the
dma_rst_n signal resets the DMAC.
Related Information
Security Usage
Describes how the security state of the irq[x] signals affects how the DMAC executes the DMAWFE and
DMASEV instructions.
How to Set the Security State for a Peripheral Request Interface
The DMAC provides the signals to enable you to assign each peripheral request interface to a security state.
The boot_periph_ns[31:0] signals connect to the system manager. Before taking the DMA out of
reset, you should program the boot_periph_ns[31:0] signals through the system manager to control
which peripheral interfaces are secure.
Note: The DMAC samples the boot_periph_ns[31:0] bits immediately after it comes out of reset,
and then ignores them until the next reset. When set, the security state of each peripheral request
interface remains constant, until a state transition on the dma_rst_n signal resets the DMAC.
Related Information
Security Usage
Describes the effect of the security state of the peripheral request interfaces on the execution of the DMAWFP,
DMALDP, DMASTP, or DMAFLUSHP instructions by a DMA channel thread.
Altera Corporation
on page 16-18
on page 16-18
on page 16-19
on page 16-19
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2013.12.30
DMA Controller
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