Calibration Block - Altera Cyclone V Device Handbook

CV-53001
2013.05.06
Figure 1-19: Clock Divider for a Transceiver Channel in Cyclone V Devices
Both types of clock dividers can divide the serial clock input to provide the parallel and serial clocks for the
serializer in the channel if you use clocks from the clock lines or transmit PLLs. The central clock divider
can additionally drive the x6 clock lines used to bond multiple channels.
In bonded channel configurations, both types of clock dividers can feed the serializer with the parallel and
serial clocks directly, without dividing them from the x6 or xN clock lines.
Related Information
Transceiver Clocking in Cyclone V Devices

Calibration Block

The calibration block calibrates the differential OCT resistance and analog circuitry in the transceiver PMA
to ensure the functionality is independent of PVT.
It is also used for duty cycle calibration of the clock line at serial data rates ≥ 4.9152 Gbps.
There is only one calibration block available for the Cyclone V transceiver PMA. It is located on the top left
of the device (same side as the transceiver channels).
Transceiver Architecture in Cyclone V Devices
Send Feedback
x6 Clock Lines (1)
xN Clock Lines (1)
x1 Clock Lines (1)
(1, 2, 4, 8)
Fractional PLL
CMU PLL (2)
To x6 Clock Lines (3)
Notes:
1. For information about the x1, x6, and xN clock lines, refer to Transceiver Clocking in Cyclone V Devices.
2. Only from the channel PLL in the same transceiver channel configured as a CMU PLL.
3. Applicable for central clock dividers only (clock dividers in channels 1 and 4).
4. The PCIe rateswitch circuit allows dynamic switching between Gen2 and Gen1 line rates in a PCIe Gen2 design.
5. The divider settings are configured automatically depending on the serialization factor. The selected divider setting is half
of the serialization factor.
PCIe Rateswitch
/N
(4, 5, 8, 10)
Circuit
PCIe Rateswitch
Control (4)
Calibration Block
To Serializer
/S
Serial Clock
(5)
Serial and Parallel
Clocks
1-25
Altera Corporation