Altera Cyclone V Device Handbook page 928

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2013.12.30
synchronized to the l4_main_clk domain, and then it is edge detected; this synchronization requires
three l4_main_clk periods. †
If the slave device is transmit and receive, the minimum frequency of l4_main_clk is eight times the
maximum expected frequency of the bit-rate clock from the master device (sclk_in). This ensures that
data on the master rxd line is stable before the master shift control logic captures the data. †
The frequency ratio restrictions between the bit-rate clock sclk_in and the SPI slave peripheral clock are
as follows: †
• Slave (receive only): Fl4_main_clk >= 6 x (maximum Fsclk_in) †
• Slave: Fl4_main_clk >= 8 x (maximum Fsclk_in) †
Transmit and Receive FIFO Buffers
There are two 16-bit FIFO buffers, a transmit FIFO buffer and a receive FIFO buffer, with a depth of 256.
Data frames that are less than 16 bits in size must be right-justified when written into the transmit FIFO
buffer. The shift control logic automatically right-justifies receive data in the receive FIFO buffer. †
Each data entry in the FIFO buffers contains a single data frame. It is impossible to store multiple data frames
in a single FIFO buffer location; for example, you may not store two 8-bit data frames in a single FIFO buffer
location. If an 8-bit data frame is required, the upper 8-bits of the FIFO buffer entry are ignored or unused
when the serial shifter transmits the data. †
The transmit and receive FIFO buffers are cleared when the PI controller is disabled (SSIENR=0) or reset.
The transmit FIFO buffer is loaded by write commands to the SPI data register (DR). Data are popped
(removed) from the transmit FIFO buffer by the shift control logic into the transmit shift register. The
transmit FIFO buffer generates a transmit FIFO empty interrupt request when the number of entries in the
FIFO buffer is less than or equal to the FIFO buffer threshold value. The threshold value, set through the
register TXFTLR, determines the level of FIFO buffer entries at which an interrupt is generated. The threshold
value allows you to provide early indication to the processor that the transmit FIFO buffer is nearly empty.
A Transmit FIFO Overflow Interrupt is generated if you attempt to write data into an already full transmit
FIFO buffer. †
Data are popped from the receive FIFO buffer by read commands to the SPI data register (DR). The receive
FIFO buffer is loaded from the receive shift register by the shift control logic. The receive FIFO buffer
generates a receive FIFO full interrupt request when the number of entries in the FIFO buffer is greater than
or equal to the FIFO buffer threshold value plus one. The threshold value, set through register RXFTLR,
determines the level of FIFO buffer entries at which an interrupt is generated. †
The threshold value allows you to provide early indication to the processor that the receive FIFO buffer is
nearly full. A Receive FIFO Overrun Interrupt is generated when the receive shift logic attempts to load data
into a completely full receive FIFO buffer. However, the newly received data are lost. A Receive FIFO
Underflow Interrupt is generated if you attempt to read from an empty receive FIFO buffer. This alerts the
processor that the read data are invalid. †
Related Information
Reset Manager
For more information, refer to theReset Manager chapter.
SPI Interrupts
The SPI controller supports combined interrupt requests, which can be masked. The combined interrupt
request is the ORed result of all other SPI interrupts after masking. All SPI interrupts have active-high polarity
level. The SPI interrupts are described as follows: †
SPI Controller
Send Feedback
on page 3-1
Transmit and Receive FIFO Buffers
19-5
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