Altera Cyclone V Device Handbook page 519

4-8
Master to Slave Connectivity Matrix
Masters
FPGA-to-HPS Bridge
DMA
EMAC 0/1
USB OTG 0/1
Altera Corporation
Connected Slaves
• L4 SP Bus Slaves
• L4 MP Bus Slaves
• L4 OSC1 Bus Slaves
• L4 MAIN Bus Slaves
• L4 SPIM Bus Slaves
• Lightweight HPS-to-FPGA Bridge
• USB OTG 0/1 CSR
• NAND CSR
• NAND Command and Data
• Quad SPI Flash Data
• ACP ID Mapper Data
• STM
• On-Chip RAM
• SDRAM Controller Subsystem L3 Data
• L4 SP Bus Slaves
• L4 MP Bus Slaves
• L4 OSC1 Bus Slaves
• L4 MAIN Bus Slaves
• L4 SPIM Bus Slaves
• Lightweight HPS-to-FPGA Bridge
• USB OTG 0/1 CSR
• NAND CSR
• NAND Command and Data
• Quad SPI Flash Data
• FPGA Manager
• HPS-to-FPGA Bridge
• ACP ID Mapper Data
• STM
• On-Chip RAM
• SDRAM Controller Subsystem L3 Data
• HPS-to-FPGA Bridge
• ACP ID Mapper Data
• On-Chip RAM
• SDRAM Controller Subsystem L3 Data
• HPS-to-FPGA Bridge
• ACP ID Mapper Data
• On-Chip RAM
• SDRAM Controller Subsystem L3 Data
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2013.12.30
Interconnect
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