Altera Cyclone V Device Handbook page 874

cv_54017
2013.12.30
Initialization for the EMAC
1. Write to Register 0 (Bus Mode Register) to set Host bus access parameters. †
2. Write to Register 7 (Interrupt Enable Register) to mask unnecessary interrupt causes. †
3. Create the transmit and receive descriptor lists, and then write to DMA Register 3 (Receive Descriptor
List Address Register) and Register 4 (Transmit Descriptor List Address Register), providing the DMA
with the starting address of each list. †
4. Write to Register 1 (MAC Frame Filter), Register 2 (Hash Table High Register), and Register 3 (Hash
Table Low Register) for desired filtering options. †
5. Write to Register 1 (MAC Frame Filter) to configure the operating mode and enable the transmit operation
(Bit 3: Transmitter Enable). The PS and DM bits are set based on the auto-negotiation result (read from
the PHY). †
6. Write to Register 6 (Operation Mode Register) to set Bits 13 and 1 to start transmission and reception. †
7. Write to Register 0 (MAC Configuration Register) to enable the receive operation (Bit 2: Receiver Enable). †
The transmit and receive engines enter the Running state and attempt to acquire descriptors from the
respective descriptor lists. The receive and transmit engines then begin processing receive and transmit
operations. The transmit and receive processes are independent of each other and can be started or stopped
separately. †
Host Bus Burst Access
The DMA attempts to execute fixed-length Burst transfers on the master interface if configured to do so
through FB bit of Register 0 (Bus Mode Register). The maximum Burst length is indicated and limited by
the PBL field (Bits [13:8]) Register 0 (Bus Mode Register). The receive and transmit descriptors are always
accessed in the maximum possible (limited by PBL or 16 * 8/bus width) burst-size for the 16- bytes to be
read.
The transmit DMA initiates a data transfer only when sufficient space to accommodate the configured burst
is available in MTL transmit FIFO buffer or the number of bytes till the end of frame (when it is less than
the configured burst-length). The DMA indicates the start address and the number of transfers required to
the master interface. When the interface is configured for fixed-length burst, then it transfers data using the
best combination of INCR4, 8, or 16 and SINGLE transactions. Otherwise (no fixed-length burst), it transfers
data using INCR (undefined length) and SINGLE transactions.
The receive DMA initiates a data transfer only when sufficient data to accommodate the configured burst
is available in MTL receive FIFO buffer or when the end of frame (when it is less than the configured burst-
length) is detected in the receive FIFO buffer. The DMA indicates the start address and the number of
transfers required to the master interface. When the interface is configured for fixed-length burst, then it
transfers data using the best combination of INCR4, 8, or 16 and SINGLE transactions. If the end-of frame
is reached before the fixed-burst ends on the interface, then dummy transfers are performed in order to
complete the fixed-burst. Otherwise (FB bit of Register 0 (Bus Mode Register) is reset), it transfers data using
INCR (undefined length) and SINGLE transactions.
When the interface is configured for address-aligned beats, both DMA engines ensure that the first burst
transfer initiated is less than or equal to the size of the configured PBL. Thus, all subsequent beats start at
an address that is aligned to the configured PBL. The DMA can only align the address for beats up to size
16 (for PBL > 16), because the interface does not support more than INCR16.
Host Data Buffer Alignment
The transmit and receive data buffers do not have any restrictions on start address alignment. For example,
in systems with 32-bit memory, the start address for the buffers can be aligned to any of the four bytes.
However, the DMA always initiates transfers with address aligned to the bus width with dummy data for
the byte lanes not required. This typically happens during the transfer of the beginning or end of an Ethernet
Ethernet Media Access Controller
Send Feedback
Initialization for the EMAC
Altera Corporation
17-25