Document Revision History - Altera Cyclone V Device Handbook

3-18

Document Revision History

Figure 3-16: 27-Bit Systolic FIR Mode for Cyclone V Devices
dataa_y0[25..0]
dataa_z0[25..0]
dataa_x0[26..0]
COEFSELA[2..0]
Document Revision History
Date
January 2014
May 2013
December 2012
Altera Corporation
Pre-Adder
26
+/-
26
27
3
Version
2014.01.10 Corrected variable-precision DSP block, 27 x 27 multiplier, 18 x 18
multiplier adder mode and 18 x 18 multiplier adder summed with 36
bit input for Cyclone V SE A4 from 58 to 84.
Corrected 18 x 18 multiplier for Cyclone V SE A4 from 116 to 168.
Corrected 9 x 9 multiplier for Cyclone V SE A4 from 174 to 252.
2013.05.06 Added link to the known document issues in the Knowledge Base.
Moved all links to the Related Information section of respective topics
for easy reference.
Updated the variable DSP blocks and multipliers counts for the
Cyclone V SX device variants.
2012.12.28 Added resources for Cyclone V devices.
Updated design considerations for Cyclone V devices in operational
modes.
Updated Figure 3-10, changed 37 to 38.
Updated Figure 3-11, changed 37 to 38 and changed Result[36..0] to
Result [37..0].
Multiplier
27
x
Internal
Coefficient
27-bit Systolic FIR
Changes
Variable Precision DSP Blocks in Cyclone V Devices
chainin[63..0]
64
+/-
+
Adder
Chainout adder or
accumulator
Send Feedback
CV-52003
2014.01.10
64
chainout[63..0]