Receiver Mode In Cyclone V Devices - Altera Cyclone V Device Handbook

CV-52005
2014.01.10
Figure 5-40: Receiver Data Realignment Rollover
This figure shows a preset value of four bit-times before rollover occurs. The
one
rx_outclock
Deserializer
You can statically set the deserialization factor to x4, x5, x6, x7, x8, x9, or x10 by using the Quartus II software.
You can bypass the deserializer in the Quartus II MegaWizard Plug-In Manager to support DDR (x2) or
SDR (x1) operations, as shown in the following figure.
Figure 5-41: Deserializer Bypass
The IOE contains two data input registers that can operate in DDR or SDR mode. In DDR mode,
clocks the IOE register. In SDR mode, data is directly passed through the IOE. In SDR and DDR modes, the
data width from the IOE is 1 and 2 bits, respectively.

Receiver Mode in Cyclone V Devices

The Cyclone V devices support the LVDS receiver mode.
LVDS Receiver Mode
Input serial data is registered at the rising edge of the serial
left and right PLLs.
I/O Features in Cyclone V Devices
Send Feedback
cycle to indicate that rollover has occurred.
rx_inclock
rx_channel_data_align
rx_outclock
rx_cda_max
IOE supports SDR, DDR, or non-registered datapath
2
10
rx_out
Deserializer
10
FPGA
Fabric
rx_outclock
IOE
Bit Slip
DOUT DIN DOUT DIN
diffioclk
2
(LOAD_EN,
diffioclk)
3 (LVDS_LOAD_EN,
LVDS_diffioclk, rx_outclock)
Fractional PLL
Note: Disabled blocks and signals are grayed out
LVDS_diffioclk
Deserializer
signal pulses for
rx_cda_max
LVDS Receiver
+ rx_in
–
rx_inclock / tx_inclock
clock that is produced by the
Altera Corporation
5-67
rx_inclock