Plls And Clocking - Altera Cyclone V Device Handbook

5-12
Mixing Voltage-Referenced and Non-Voltage Referenced I/O Standards
Mixing Voltage-Referenced and Non-Voltage Referenced I/O Standards
An I/O bank can support voltage-referenced and non-voltage-referenced pins by applying each of the rule
sets individually.
Examples:
An I/O bank can support SSTL-18 inputs and outputs, and 1.8 V inputs and outputs with a 1.8 V V
and a 0.9 V V
An I/O bank can support 1.5 V standards, 1.8 V inputs (but not outputs), and 1.5 V HSTL I/O standards
with a 1.5 V V

PLLs and Clocking

The Cyclone V device family supports fractional PLLs on each side of the device. You can use fractional
PLLs to reduce the number of oscillators and the clock pins used in the FPGA by synthesizing multiple clock
frequencies from a single reference clock source.
The corner fractional PLLs can drive the LVDS receiver and driver channels. However, the clock tree network
cannot cross over to different I/O regions. For example, the top left corner fractional PLL cannot cross over
to drive the LVDS receiver and driver channels on the top right I/O bank. The Quartus II compiler
automatically checks the design and issues an error message if the guidelines are not followed.
Related Information
High-Speed Differential I/O Locations
PLL locations that are available for each device.
Guideline: Use PLLs in Integer PLL Mode for LVDS
Guideline: Use PLLs in Integer PLL Mode for LVDS
To drive the LVDS channels, you must use the PLLs in integer PLL mode. The corner PLLs can drive the
LVDS receiver and transmitter channels.
Guideline: Reference Clock Restriction for LVDS Application
You must use the dedicated reference clock pin of the same I/O bank used by the data channel. For I/O
banks without a dedicated reference clock pin, use the reference clock pin in the I/O bank listed in the
following table.
Altera Corporation
.
REF
and 0.75 V V .
CCIO REF
on page 5-52
on page 5-12
I/O Features in Cyclone V Devices
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CV-52005
2014.01.10
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