Jtag Multi-Device Configuration; Config_Io Jtag Instruction - Altera Cyclone V Device Handbook

CV-52007
2014.01.10

JTAG Multi-Device Configuration

You can configure multiple devices in a JTAG chain.
Pin Connections and Guidelines
Observe the following pin connections and guidelines for this configuration setup:
Isolate the
One JTAG-compatible header is connected to several devices in a JTAG chain. The number of devices
in the chain is limited only by the drive capability of the download cable.
If you have four or more devices in a JTAG chain, buffer the
buffer. You can also connect other Altera devices with JTAG support to the chain.
JTAG-chain device programming is ideal when the system contains multiple devices or when testing
your system using the JTAG boundary-scan testing (BST) circuitry.
Using a Download Cable
The following figure shows a multi-device JTAG configuration.
Figure 7-19: JTAG Configuration of Multiple Devices Using a Download Cable
Download Cable
10-Pin Male Header
(JTAG Mode)
Pin 1
Related Information
AN 656: Combining Multiple Configuration Schemes
Provides more information about combining JTAG configuration with other configuration schemes.

CONFIG_IO JTAG Instruction

The
CONFIO_IO
during device configuration. When you issue this instruction, it interrupts configuration and allows you to
issue all JTAG instructions. Otherwise, you can only issue the
Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
Send Feedback
and
CONF_DONE nSTATUS
If you only use the JTAG configuration, connect nCONFIG to V CCPGM and MSEL[4..0]
to GND. Pull DCLK either high or low, whichever is convenient on your board. If you are
using JTAG in conjunction with another configuration scheme, connect MSEL[4..0],
Connect the pull-up
nCONFIG, and DCLK based on the selected configuration scheme.
resistor V .
CCPD
FPGA Device
V
CCPGM
10 kΩ
V
CCPD
nSTATUS
nCONFIG
DCLK
CONF_DONE
V
CCPD
MSEL[4..0]
nCE
GND
TDI
V
IO
V
CCPD
TMS
1 kΩ
The resistor value can vary from 1 kΩ to 10
kΩ. Perform signal integrity analysis to
select the resistor value for your setup.
JTAG instruction allows you to configure the I/O buffers using the JTAG port before or
pins to allow each device to enter user mode independently.
FPGA Device
V V
CCPGM CCPGM
10 kΩ 10 kΩ
nSTATUS
nCONFIG
DCLK
CONF_DONE
MSEL[4..0]
nCE
GND
TDI
TDO
TCK TMS TCK
BYPASS
JTAG Multi-Device Configuration
, , and pins with an on-board
TCK TDI TMS
FPGA Device
V V V
CCPGM CCPGM
10 kΩ 10 kΩ 10 kΩ
nSTATUS
nCONFIG
DCLK
CONF_DONE
MSEL[4..0]
nCE
GND
TDI
TDO
TDO
TMS TCK
, , and JTAG instructions.
IDCODE SAMPLE
7-27
CCPGM
Altera Corporation