Types Of Clock Regions - Altera Cyclone V Device Handbook

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Types of Clock Regions

Figure 4-7: Hierarchical Clock Networks in Each Spine Clock Per Quadrant
Clock output from the PLL
that drives into the SCLKs.
There are up to 12 PCLKs that can drive
the SCLKs in each spine clock per
quadrant in the largest device.
There are up to 22 RCLKs that can drive
the SCLKs in each spine clock per
quadrant in the largest device.
Types of Clock Regions
This section describes the types of clock regions in Cyclone V devices.
Entire Device Clock Region
To form the entire device clock region, a source drives a signal in a GCLK network that can be routed through
the entire device. The source is not necessarily a clock signal. This clock region has the maximum insertion
delay when compared with other clock regions, but allows the signal to reach every destination in the device.
It is a good option for routing global reset and clear signals or routing clocks throughout the device.
Regional Clock Region
To form a regional clock region, a source drives a signal in a RCLK network that you can route throughout
one quadrant of the device. This clock region provides the lowest skew in a quadrant. It is a good option if
all the destinations are in a single quadrant.
Dual-Regional Clock Region
To form a dual-regional clock region, a single source (a clock pin or PLL output) generates a dual-regional
clock by driving two RCLK networks (one from each quadrant). This technique allows destinations across
two adjacent device quadrants to use the same low-skew clock. The routing of this signal on an entire side
has approximately the same delay as a RCLK region. Internal logic can also drive a dual-regional clock
network.
Dual-regional clock region is only supported for quadrant 3 and quadrant 4 in Cyclone V SE, SX, and ST
devices.
Altera Corporation
16
GCLK
5
PLL Feedback Clock
12
PCLK
22
RCLK
SCLK 30
For Cyclone V E A5 device, Cyclone V GX C3, C4, and C5 devices, and
Cyclone V GT D5 device, only 18 SCLKs are available in quadrant 3 and quadrant
4, which are SCLK[0,1], SCLK[5..10], SCLK[12..15], and SCLK[20..25].
Clock Networks and PLLs in Cyclone V Devices
9
Column I/O clock: clock that drives
the I/O column core registers
and I/O interfaces.
2
Core reference clock: clock that feeds
into the PLL as the PLL reference clock.
6
Row clock: clock source to the LAB,
memory blocks, and row I/O interfaces
in the core row.
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CV-52004
2014.01.10