True Lvds Buffers In Cyclone V Devices - Altera Cyclone V Device Handbook

CV-52005
2014.01.10
Figure 5-34: LVDS SERDES
The preceding figure shows a shared PLL between the transmitter and receiver. If the transmitter and receiver
do not share the same PLL, you require two fractional PLLs. In single data rate (SDR) and double data rate
(DDR) modes, the data width is 1 and 2 bits, respectively.
Note: For the maximum data rate supported by the Cyclone V devices, refer to the device overview.
Related Information
Cyclone V Device Overview
LVDS SERDES Transmitter/Receiver (ALTLVDS_TX and ALTLVDS_RX) Megafunction User Guide
Provides a list of the LVDS transmitter and receiver ports and settings using ALTLVDS.
Guideline: Use PLLs in Integer PLL Mode for LVDS

True LVDS Buffers in Cyclone V Devices

The Cyclone V device family supports LVDS on all I/O banks:
Both row and column I/Os support true LVDS input buffers with R
Cyclone V devices offer single-ended I/O reference clock support for the fractional PLL that drives the
SERDES.
Note: True LVDS output buffers cannot be tri-stated.
The following tables list the number of true LVDS buffers supported in Cyclone V devices with these
conditions:
The LVDS channel count does not include dedicated clock pins.
I/O Features in Cyclone V Devices
Send Feedback
10
tx_in
10 bits
tx_coreclock
maxiumum
data width
10
rx_out
10
FPGA
Fabric
rx_outclock
LVDS Clock Domain
2
IOE
IOE supports SDR, DDR, or non-registered datapath
Serializer
DIN DOUT
(LVDS_LOAD_EN, diffioclk, tx_coreclock)
3
IOE supports SDR, DDR, or non-registered datapath
2
IOE
Deserializer Bit Slip
DOUT DIN DOUT
2
(LOAD_EN,
diffioclk)
3 (LVDS_LOAD_EN,
Fractional PLL
on page 5-12
True LVDS Buffers in Cyclone V Devices
+
–
LVDS Transmitter
LVDS Receiver
DIN
diffioclk
LVDS_diffioclk, rx_outclock)
rx_inclock / tx_inclock
OCT and true LVDS output buffers.
D
5-55
tx_out
+ rx_in
–
Altera Corporation