Altera Cyclone V Device Handbook page 306

CV-53001
2013.05.06
Deserializer
The deserializer block clocks in serial input data from the receiver buffer using the high-speed serial recovered
clock and deserializes the data using the low-speed parallel recovered clock. The deserializer forwards the
deserialized data to the receiver PCS.
The deserializer supports 8, 10, 16, and 20 bits of deserialization factors.
Figure 1-15: Deserializer Operation with a 10-bit Deserialization Factor
Figure 1-16: Deserializer Bit Order with 10-bit Deserialization Factor
The serial stream (0101111100) is deserialized to a 10'h17C value. The serial data is received LSB to MSB.
Parallel Clock
Serial Clock
Clock-slip
Word alignment in the PCS may contribute up to one parallel clock cycle of latency uncertainty. The clock-
slip feature allows word alignment operation with a reduced latency uncertainty by performing the word
alignment function in the deserializer. Use the clock slip feature for applications that require deterministic
latency.
Transceiver Architecture in Cyclone V Devices
Send Feedback
Received Data
Serial Recovered
Clock from CDR
Parallel Recovered
Clock from CDR
datain 0 0 1 1 1 1
dataout
D9 D9
D8 D8
D7 D7
D6 D6
D5 D5
D4 D4
D3 D3
D2 D2
D1 D1
D0 D0
1 0 1 0 1 1 0 0 0
0101111100
Deserializer
10
To RX PCS
0 0 1 0 1
1010000011
1-19
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