Altera Cyclone V Device Handbook page 305

1-18
Programmable CTLE and DC Gain
Figure 1-14: Receiver Buffer Block Diagram in Cyclone V Devices
Modifying programmable values within receiver input buffers can be performed by a single reconfiguration
controller for the entire FPGA, or multiple reconfiguration controllers if desired. Within each transceiver
bank (three-transceiver channels) a maximum of one reconfiguration controller is allowed. There is only
one slave interface to all PLLs and PMAs within each transceiver bank. Therefore, many transceiver banks
can be connected to a single reconfiguration controller, but only one reconfiguration controller can be
connected to the transceiver bank (three-transceiver channels).
Note: A maximum of one reconfiguration controller is allowed per transceiver bank.
Programmable CTLE and DC Gain
Each receiver buffer has a single-tap programmable equalization circuit that boosts the high-frequency gain
of the incoming signal, thereby compensating for the low-pass filter effects of the physical medium. The
amount of high-frequency gain required depends on the loss characteristics of the physical medium. The
equalization circuitry provides up to 4 dB of high-frequency boost.
Each receiver buffer also supports the programmable DC gain circuitry that provides an equal boost to the
incoming signal across the frequency spectrum. The DC gain circuitry provides up to 3 dB of gain setting.
Programmable Receiver V
The receiver buffers have on-chip biasing circuitry to establish the required V
circuitry supports a V
On-chip biasing circuitry is available only if you select one of the termination logic options in order to
configure OCT. If you select external termination, you must implement off-chip biasing circuitry to establish
V at the receiver input buffer.
CM
Programmable Receiver Differential On-Chip Termination
The receiver buffers support optional differential OCT resistances of 85, 100, 120, and 150 Ω . The resistance
is adjusted by the on-chip calibration circuit during calibration, which compensates for PVT changes.
Signal Threshold Detection Circuitry
In a PCIe and SATA/SAS configuration, the signal threshold detection circuitry will be enabled to detect
the present of incoming signal.
The signal threshold detection circuitry senses whether the signal level present at the receiver input buffer
is above the signal detect threshold voltage you specified.
Altera Corporation
High-speed
Differential
Rx
– +
Receiver
VCM
Channel
Input Pins
CM
setting of 0.8 V.
CM
CTLE
and DC Gain
To CDR PLL
Circuitry
Signal
Detect
Circuitry
at the receiver input. The
CM
Transceiver Architecture in Cyclone V Devices
CV-53001
2013.05.06
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