Mfifo Buffer Usage Overview - Altera Cyclone V Device Handbook

16-44

MFIFO Buffer Usage Overview

Syntax
SP Source protection
SC Source cache
DA Destination address increment. Sets the value of
awburst[0]
DS Destination burst size in bits. Sets the value of
awsize[2:0]
DB Destination burst length. Sets the value of
awlen[3:0]
DP Destination protection
DC Destination cache
ES Endian swap size, in bits
MFIFO Buffer Usage Overview
About MFIFO Buffer Usage Overview
The MFIFO buffer is a shared resource that is utilized on a first-come, first-served basis by all currently
active channels. To a program, it appears as a set of variable-depth parallel FIFO buffers, one per channel,
with the restriction that the total depth of all the Fifes cannot exceed the buffer depth, 512. The width of the
AXI master interface is the same as the MFIFO buffer width.
The DMAC is capable of realigning data from the source to the destination. For example, the DMAC shifts
the data by two byte lanes when it reads a word from address 0x103 and writes to address 0x205. All byte
manipulations occur when data enters the MFIFO buffer, as a result of an AXI read due to a DMALD
instruction, so that the DMAC does not need to manipulate the data when it removes it from the MFIFO
buffer, as a result of an AXI write due to a DMAST instruction. Therefore the storage and packing of the data
in the MFIFO buffer is determined by the destination address and transfer characteristics.
When a program specifies that incrementing transactions are to be performed to the destination, the DMAC
packs data into the MFIFO buffer to minimize the usage of the MFIFO buffer entries. For example, the
DMAC packs two 32-bit words into a single entry in the MFIFO buffer when the DMAC has a 64-bit AXI
data bus and the program uses a source address of 0x100, and destination address of 0x200.
(39)
You must use decimal values when programming this immediate value
(40)
Because the DMAC ties ARCACHE[3] LOW, the assembler always sets bit 3 to 0 and uses bits [2:0] of your
chosen value for SC.
(41)
Because the DMAC ties AWCACHE[2] LOW, the assembler always sets bit 2 to 0 and uses bit [3] and bits
[1:0] of your chosen value for DC.
Altera Corporation
Description Options
(39)
0 to 7
(39)(40)
0 to 15
I = Increment
F = Fixed
8, 16, 32, or 64
1 to 16
(39)
0 to 7
(39)(41)
0 to 15
8, 16, 32, or 64
cv_54016
2013.12.30
Default
0
0
I
8
1
0
0
8
DMA Controller
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