Altera Cyclone V Device Handbook page 664

10-26
Main+Spare Area Transfer Mode
Main+Spare Area Transfer Mode
In main+spare area transfer mode, the NAND flash controller expects software to format a page as shown
in following figure. When ECC is enabled during a write operation, the flash controller-generated ECC check
bits replace the ECC check bit data provided by software. During read operations, the flash controller forwards
the ECC check bits from the device to the host. If ECC is disabled, page data received from the software is
written to the device, and read data received from the device is forwarded to the host.
Figure 10-4: Main+Spare Area Transfer Mode Programming Model for ECC
Sector 0 ECC0
Preserving Bad Block Markers
When flash device manufacturers test their devices at the time of manufacture, they mark any bad device
blocks that are found. Each bad block is marked at specific, known offsets, typically at the base of the spare
area. A bad block marker is any byte value other than 0xFF (the normal state of erased flash).
Bad block markers can be overwritten by the last sector data in a page when ECC is enabled. This happens
because the NAND flash controller also uses the main area of a page to store ECC information, which causes
the last sector to spill over into the spare area. It is necessary for the system to preserve the bad block
information prior to writing data, to ensure the correct identification of bad blocks in the flash device.
You can configure the NAND flash controller to skip over a specified number of bytes when it writes the
last sector in a page to the spare area. This option allows the flash controller to preserve bad block markers.
To use this option, write the desired offset to the spare_area_skip_bytes register in the config
group. For example, if the device page size is 2 KB, and the device manufacturer stores the bad block markers
in the first two bytes in the spare area, set the spare_area_skip_bytes register to 2. When the flash
controller writes the last sector of the page that overlaps with the spare area, it starts at offset 2 in the spare
area, skipping the bad block marker at offset 0. A value of 0 (default) specifies that no bytes are skipped. The
value of spare_area_skip_bytes must be an even number. For example, if the bad block marker is
a single byte, set spare_area_skip_bytes to 2.
In main area transfer mode, the NAND flash controller does not skip the bad block marker. Instead, it
overrides the bad block marker with the value programmed in the spare_area_marker register in the
config group. This 8-bit register is used in conjunction with the spare_area_skip_bytes register
in the config group to determine which bytes in the spare area of a page should be written with a the new
marker value. For example, to mark a block as good set the spare_area_marker register to 0xFF and
set the spare_area_skip_bytes register to the number of bytes that the marker should be written to,
starting from the base of the spare area.
In the spare area transfer mode, the NAND flash controller ignores the spare_area_skip_bytes and
spare_area_marker registers. The flash controller transfers the data exactly as received from the host
or device.
In the main+spare area transfer mode, the NAND flash controller starts writing the last sector in a page into
the spare area, starting at the offset specified in the spare_area_skip_bytes register. However, the
area containing the bad block identifier information is overwritten by the data the host writes into the page.
The host writes both the data sectors and the bad block markers. The flash controller depends on the host
software to set up the bad block markers properly before writing the data.
For more information about the formatting of this data, refer to Main+Spare Area Transfer Mode.
Altera Corporation
Sector 1 ECC1 Sector 2 ECC2 Sector 3 ECC3
2013.12.30
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NAND Flash Controller
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