Altera Cyclone V Device Handbook page 807

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2013.12.30
Table 16-1: Peripheral Request Interface Mapping
Peripheral
FPGA 0
FPGA 1
FPGA 2
FPGA 3
FPGA 4
FPGA 5
FPGA 6
FPGA 7
2
I C 0 TX
2
I C 0 RX
2
I C 1 TX
2
I C 1 RX
2
I C 2 TX (EMAC)
2
I C 2 RX (EMAC)
2
I C 3 TX (EMAC)
2
I C 3 RX (EMAC)
Request Acceptance Capability
The DMAC can accept one active request for each peripheral request interface. An active request exists when
the DMAC has not started the requested AXI data transfers.
Peripheral Length Management
A peripheral can control the quantity of data that a DMA cycle contains, without the DMAC being aware
of how many data transfers it contains. The peripheral controls the DMA cycle in one of the following ways:
• Selects a single transfer
• Selects a burst transfer
• Notifies the DMAC when it commences the final request in the current series
DMA Controller
Send Feedback
Request Protocol
Interface
ID
0 Synopsys
1 Synopsys
2 Synopsys
3 Synopsys
4 Synopsys
5 Synopsys
6 Synopsys
7 Synopsys
8 Synopsys
9 Synopsys
10 Synopsys
11 Synopsys
12 Synopsys
13 Synopsys
14 Synopsys
15 Synopsys
Request Acceptance Capability
Peripheral Request
Interface
ID
SPI Master 0 TX 16
SPI Master 0 RX 17
SPI Slave 0 TX 18
SPI Slave 0 RX 19
SPI Master 1 TX 20
SPI Master 1 RX 21
SPI Slave 1 TX 22
SPI Slave 1 RX 23
Quad SPI Flash 24
TX
Quad SPI Flash 25
RX
STM 26
Reserved 27
UART 0 TX 28
UART 0 RX 29
UART 1 TX 30
UART 1 RX 31
16-11
Protocol
Synopsys
Synopsys
Synopsys
Synopsys
Synopsys
Synopsys
Synopsys
Synopsys
ARM
ARM
ARM
Synopsys
Synopsys
Synopsys
Synopsys
Synopsys
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