Altera Cyclone V Device Handbook page 507

cv_54003
2013.12.30
Figure 3-4: Warm Reset Timing Diagram
h2f_pending_rst_req_n (2)
(and other wait
request handshakes)
f2h_pending_rst_ack_n
safe_mode_req
cm_rm_safe_mode_ack
miscmod_rst_n
mpu_scu_rst_n
mpu_periph_rst_n
peripheral resets
(1) Cold reset can be initiated from several other sources: FPGA CB, FPGA fabric, modules in the HPS, and reset pins.
(2) When the nRSTpin count is zero, the 256 cycle stretch count is skipped and the start of the deassertion sequence is determined by the safe mode
acknowledge signal or the userreleasing the warm reset button, whichever occurs later.
The cold and warm reset sequences consist of different reset assertion sequences and the same deassertion
sequence. The following sections describe the sequences.
Related Information
Clock Manager
For more information about safe mode, refer to the Clock Manager chapter.
Cold Reset Assertion Sequence
The following list describes the assertion steps for cold reset shown in the cold Reset Timing Diagram:
1. Assert module resets.
2. Wait for 32 cycles. Deassert clock manager cold reset.
3. Wait for 96 cycles (so clocks can stabilize).
4. Proceed to the "Cold and Warm Reset Deassertion Sequence" section using the following link.
Related Information
Cold and Warm Reset Deassertion Sequence
Reset Manager
Send Feedback
nRST pin (1)
l3_rst_n
mpu_clkoff
mpu_rst_n[0]
mpu_wd_rst_n
mpu_l2_rst_n
8
on page 2-1
nRST Pin Count (3)
on page 3-12
Cold Reset Assertion Sequence
256 (3)
100 200
3-11
Software
brings out
of reset
32 32
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