Clocks; Resets; Interrupts - Altera Cyclone V Device Handbook

cv_54021
2013.12.30
with the IIR_FCR.FIFOE bit, automatic flow control is also disabled regardless of any other settings.
When auto CTS is not implemented or disabled, the transmitter is unaffected by cts_n.†
Figure 21-3: Automatic CTS Timing
cts_n

Clocks

The UART controller is connected to the l4_sp_clk clock. The clock input is driven by the clock manager.
Related Information
Clock Manager
For more information, refer to the Clock Manager chapter.

Resets

The UART controller is connected to the uart_rst_n reset signal. The reset manager drives the signal
on a cold or warm reset.
Related Information
Reset Manager
For more information, refer to the Reset Manager chapter.

Interrupts

The assertion of the UART interrupt output signal occurs when one of the following interrupt types are
enabled and active: †
Table 21-2: Interrupt Types and Priority †
Receiver line status
Received data available
Character timeout indication
Transmit holding register empty
You can enable the interrupt types with the interrupt enable register (IER_DLH).
Programmable THRE Interrupt
The UART has a programmable THRE interrupt mode to increase system performance. You enable the
programmable THRE interrupt mode with the interrupt enable register (IER_DLH.PTIME). When the
THRE mode is enabled, THRE interrupts and the dma_tx_req signal are active at and below a programmed
transmit FIFO buffer empty threshold level, as shown in the flowchart. †
UART Controller
Send Feedback
sout
start data bits stop
on page 2-1
on page 3-1
Interrupt Type
start data bits stop start
Disabled
Highest
Second
Second
Third
Clocks
data bits stop
Priority
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21-5