Embedded Memory Design Guidelines For Cyclone V Devices; Guideline: Consider The Memory Block Selection - Altera Cyclone V Device Handbook

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Embedded Memory Design Guidelines for Cyclone V Devices

Cyclone V GX

Cyclone V GT

Cyclone V SE

Cyclone V SX

Cyclone V ST

Embedded Memory Design Guidelines for Cyclone V Devices

There are several considerations that require your attention to ensure the success of your designs. Unless

noted otherwise, these design guidelines apply to all variants of this device family.

The Quartus II software automatically partitions the user-defined memory into the memory blocks based

on your design's speed and size constraints. For example, the Quartus II software may spread out the memory

across multiple available memory blocks to increase the performance of the design.

To assign the memory to a specific block size manually, use the RAM megafunction in the MegaWizard

Plug-In Manager.

For the memory logic array blocks (MLAB), you can implement single-port SRAM through emulation using

the Quartus II software. Emulation results in minimal additional use of logic resources.

Because of the dual-purpose architecture of the MLAB, only data input and output registers are available in

the block. The MLABs gain read address registers from the ALMs. However, the write address and read data

registers are internal to the MLABs.

Altera Corporation

RAM Bit (Kb)

Embedded Memory Blocks in Cyclone V Devices

RAM Bit (Kb)

Total RAM Bit (Kb)

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