Altera Cyclone V Device Handbook page 843

cv_54016
2013.12.30
Aligned Asymmetric Program with Multiple Stores
The following program performs four stores for each load and the source address and destination address
are aligned with the AXI data bus width.
DMAMOV CCR, SB4 SS64 DB1 DS64
DMAMOV SAR, 0x1000
DMAMOV DAR, 0x4000
DMALP 16
DMALD ; shown as a in the figure below
DMAST ; shown as b in the figure below
DMAST ; shown as c in the figure below
DMAST ; shown as d in the figure below
DMAST ; shown as e in the figure below
DMALPEND
DMAEND
Figure 16-27: Aligned Asymmetric Program with Multiple Stores
Each DMALD requires four entries and each DMAST removes one entry.
This example has a static requirement of zero MFIFO buffer entries and a dynamic requirement of four
MFIFO buffer entries.
Unaligned Transfers
Aligned Source Address to Unaligned Destination Address
In the following program, the source address is aligned with the AXI data bus width but the destination
address is unaligned. The destination address is not aligned to the destination burst size so the first DMAST
instruction removes less data than the first DMALD instruction reads. Therefore, a final DMAST of a single
word is required to clear the data from the MFIFO buffer.
DMAMOV CCR, SB4 SS64 DB4 DS64
DMAMOV SAR, 0x1000
DMAMOV DAR, 0x4004
DMALP 16
DMALD ; shown as a1, ... a, an in the figure below
DMAST ; shown as b in the figure below
DMALPEND
DMAMOV CCR, SB4 SS64 DB1 DS32
DMAST ; shown as c in the figure below
DMAEND
DMA Controller
Send Feedback
a a a
4
b b
c c
d d
0
e e
Aligned Asymmetric Program with Multiple Stores
Data from DMALD
DMALD
7
a a a a a a a a
b a a a a a a a a
c a a a a a a a a
d a a a a a a a a
Data for
e
4x DMAST
DMAST
16-47
0
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