Altera Cyclone V Device Handbook page 480

2-6
Main Clock Group
Table 2-2: Main PLL Output Assignments
PLL
Main
The counter outputs from the main PLL can have their frequency further divided by programmable dividers
external to the PLL. Transitions to a different divide value occur on the fastest output clock, one clock cycle
prior to the slowest clock's rising edge. For example, cycle 15 of the divide-by-16 divider for the main C2
output and cycle 3 of the divide-by-4 divider for the main C0 output.
The following figure shows how each counter output from the main PLL can have its frequency further
divided by programmable post-PLL dividers. Green-colored clock gating logic is directly controlled by
software writing to a register. Orange-colored clock gating logic is controlled by hardware. Orange-colored
clock gating logic allows hardware to seamlessly transition a synchronous set of clocks, for example, all the
MPU subsystem clocks.
Altera Corporation
Output Counter
C0
C1
C2
C3
C4
C5
Note: The maximum frequency depends on the speed grade of the
device.
Clock Name
osc1_clk to varies
mpu_base_clk
(1)
osc1_clk to varies
main_base_clk
(1)
osc1_clk/4 to
dbg_base_clk
mpu_base_clk/2
Up to 432 MHz
main_qspi_
base_clk
Up to 250 MHz for
main_nand_
the NAND flash
sdmmc_base_
controller and up to
clk
200 MHz for the SD/
MMC controller
osc1_clk to
cfg_h2f_
125 MHz for driving
user0_base_
configuration and
clk
100 MHz for the user
clock
Frequency Phase Shift Control
No
No
No
No
No
No
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2013.12.30
Clock Manager