Flash Controller Clocks - Altera Cyclone V Device Handbook

2-14

Flash Controller Clocks

Table 2-7: SDRAM Clock Group Clocks
Name
ddr_dqs_clk
ddr_2x_dqs_clk
ddr_dq_clk
h2f_user2_clock
Flash Controller Clocks
Flash memory peripherals can be driven by the main PLL, the peripheral PLL, or from clocks provided by
the FPGA fabric.
Figure 2-6: Flash Peripheral Clock Divide and Gating
main_nand_sdmmc_base_clk
periph_nand_sdmmc_base_clk
main_nand_sdmmc_base_clk
periph_nand_sdmmc_base_clk
Altera Corporation
SDRAM PLL C0
SDRAM PLL C1
SDRAM PLL C2
SDRAM PLL C5
f2h_periph_ref_clk
f2h_periph_ref_clk
f2h_periph_ref_clk
main_qspi_base_clk
periph_qspi_base_clk
Frequency
Clock Gate
Divide by 4
Clock Gate
Clock Gate
Constraints and Notes
Clock for MPFE, single-port
controller, CSR access, and PHY
Clock for PHY
Clock for PHY
Auxiliary user clock to the FPGA
fabric
sdmmc_clk
nand_x_clk
nand_clk
Clock Gate
qspi_clk
Clock Manager
Send Feedback
cv_54002
2013.12.30