Altera Cyclone V Device Handbook page 196

6-22
PHY Clock (PHYCLK) Networks
Figure 6-9: PHYCLK Networks in Cyclone V GX C3 Devices
Figure 6-10: PHYCLK Networks in Cyclone V E A7, A5, and A9 Devices, Cyclone V GX C4, C5, C7, and C9
Devices, and Cyclone V GT D5, D7, and D9 Devices
Altera Corporation
I/O Bank 8
Sub-Bank Sub-Bank
Left
PLL
PHYCLK Networks
FPGA Device
PHYCLK Networks
Sub-Bank Sub-Bank
I/O Bank 3
I/O Bank 8
Sub-Bank Sub-Bank
Left
PLL
PHYCLK Networks
FPGA Device
PHYCLK Networks
Left
PLL
Sub-Bank Sub-Bank
I/O Bank 3
I/O Bank 7
Sub-Bank Sub-Bank
Right
PLL
Right
PLL
Sub-Bank Sub-Bank
I/O Bank 4
I/O Bank 7
Sub-Bank Sub-Bank
Right
PLL
Right
PLL
Sub-Bank Sub-Bank
I/O Bank 4
External Memory Interfaces in Cyclone V Devices
CV-52006
2014.01.10
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