Clock - Altera Cyclone V Device Handbook

cv_54013
2013.12.30
If DCLK is selected as the clock source, software uses the DCLK count (dclkcnt) register to drive DCLK
pulses to the FPGA. Writing to the cnt field of the dclkcnt register triggers the FPGA manager to generate
the specified number of DCLK pulses. When all of the DCLK pulses have been sent, the dcntdone bit of
the DCLK status (dclkstat) register is set to 1. Software polls the dcntdone bit to know when all of the
DCLK pulses have been sent.
Note: Before another write to the dclkcnt register, software needs to write a value of 1 to the dcntdone
bit to clear the done state.
The FPGA user I/O pins are still tri-stated in this phase. When the initialization phase completes, the FPGA
releases the optional INIT_DONE pin and an external resistor pulls the pin high.
User Mode
The FPGA enters the user mode after exiting the initialization phase. The FPGA user I/O pins are no longer
tri-stated in this phase and the configured soft logic in the FPGA becomes active.
The FPGA remains in user mode until the nCONFIG pin is driven low. If the nCONFIG pin is driven low,
the FPGA reenters the reset phase. The internal oscillator is disabled in user mode, but is enabled as soon
as the nCONFIG pin is driven low.
Related Information
• Configuration, Design Security, and Remote System Upgrades
For more information about configuring the FPGA through the HPS, refer to the Configuration, Design
Security, and Remote System Upgrade appendix in the Cyclone V Device Handbook, Volume 1.
• Booting and Configuration
For more information about configuring the FPGA through the HPS, refer to the Booting and Configuration
appendix in the Cyclone V Device Handbook, Volume 3.
• Booting and Configuration Introduction
For more information about configuring the FPGA through the HPS, refer to the Booting and Configuration
appendix.

Clock

The FPGA manager has two clock input signals which are asynchronous to each other. The clock manager
generates these two clocks:
• cfg_clk the configuration slave interface clock input and also the DCLK output reference for FPGA
configuration. Enable this clock in the clock manager only when configuration is active or when the
configuration slave interface needs to respond to master requests.
• l4_mp_clk the register slave interface clock.
Related Information
Clock Manager
FPGA Manager
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