Disabling The I2C Controller; Dma Controller Operation - Altera Cyclone V Device Handbook

cv_54020
2013.12.30
Dynamic IC_TAR or IC_10BITADDR_MASTER Update
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The I C controller supports dynamic updating of the IC_TAR (bits 9:0) and IC_10BITADDR_MASTER
(bit 12) bit fields of the IC_TAR register. You can dynamically write to the IC_TAR register provided the
following conditions are met: †
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• The I C controller is not enabled (IC_ENABLE=0); †
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• The I C controller is enabled (IC_ENABLE=1); AND I
RX) operation (IC_STATUS[5]=0); AND I
(IC_CON[0]=1); AND there are no entries in the TX FIFO (IC_STATUS[2]=1) †
Master Transmit and Master Receive
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The I C controller supports switching back and forth between reading and writing dynamically. To transmit
data, write the data to be written to the lower byte of the I
(IC_DATA_CMD). The CMD bit [8] should be written to 0 for I
command may be issued by writing "don't cares" to the lower byte of the IC_DATA_CMD register, and a 1
should be written to the CMD bit.†

Disabling the I2C Controller

The register IC_ENABLE_STATUS is added to allow software to unambiguously determine when the
hardware has completely shutdown in response to the IC_ENABLE register being set from 1 to 0. †
1. Define a timer interval (ti2c_poll) equal to the 10 times the signaling period for the highest I
transfer speed used in the system and supported by the I
transfer mode is 400 Kbps, then ti2c_poll is 25 us. †
2. Define a maximum time-out parameter, MAX_T_POLL_COUNT, such that if any repeated polling
operation exceeds this maximum value, an error is reported. †
3. Execute a blocking thread/process/function that prevents any further I
by software, but allows any pending transfers to be completed.
• This step can be ignored if the I
4. The variable POLL_COUNT is initialized to zero. †
5. Set IC_ENABLE to 0. †
6. Read the IC_ENABLE_STATUS register and test the IC_EN bit (bit 0). Increment POLL_COUNT by
one. If POLL_COUNT >= MAX_T_POLL_COUNT, exit with the relevant error code. †
7. If IC_ENABLE_STATUS[0] is 1, then sleep for ti2c_poll and proceed to the previous step.
Otherwise, exit with a relevant success code. †

DMA Controller Operation

To enable the DMA controller interface on the I
(IC_DMA_CR). Writing a 1 to the TDMAE bit field of IC_DMA_CR register enables the I
handshaking interface. Writing a 1 to the RDMAE bit field of the IC_DMA_CR register enables the I
controller receive handshaking interface.†
The FIFO buffer depth (FIFO_DEPTH) for both the RX and TX buffers in the I
I2C Controller
Send Feedback
Dynamic IC_TAR or IC_10BITADDR_MASTER Update
2
C controller is NOT engaged in any Master (TX,
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C controller is enabled to operate in Master mode
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C Rx/Tx Data Buffer and Command Register
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C controller. For example, if the highest I
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C controller is programmed to operate as an I
2
C controller, you must write the DMA Control Register
2
C write operations. Subsequently, a read
2
C master transactions to be started
2
C slave only. †
2
C controller transmit
2
C controller is 64 entries.
20-17
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C
2
C
2
C
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