Altera Cyclone V Device Handbook page 192

6-18
Delay-Locked Loop
Figure 6-6: DQS Pins and DLLs in Cyclone V SX (C2, C4, C5, and C6) and ST (D5 and D6) Devices
Related Information
Cyclone V Device Pin-Out Files
Download the relevant pin tables from this web page.
Delay-Locked Loop
The delay-locked loop (DLL) uses a frequency reference to dynamically generate control signals for the delay
chains in each of the DQS pins, allowing the delay to compensate for process, voltage, and temperature
(PVT) variations. The DQS delay settings are gray-coded to reduce jitter if the DLL updates the settings.
There are a maximum of four DLLs, located in each corner of the Cyclone V devices. You can clock each
DLL using different frequencies.
The DLLs can access the two adjacent sides from its location in the device. You can have two different
interfaces with the same frequency on the two sides adjacent to a DLL, where the DLL controls the DQS
delay settings for both interfaces.
Altera Corporation
DQS
Pin
DLL
Reference
Clock
Δt
DLL to IOE
to IOE
to to
DLL
IOE IOE
Δt Δt
DLL
Reference
Clock
DQS DQS
Pin Pin
DQS
Pin
Δt
HPS I/O
HPS
to IOE
PLL
HPS Block
to IOE
to to
IOE IOE
Δt Δt
DQS Logic
Blocks
DQS DQS
Pin Pin
External Memory Interfaces in Cyclone V Devices
DLL
DQS Logic
Blocks
DQS
Δt
Pin
DQS
Δt
Pin
to DQS
Δt
IOE Pin
to
IOE
DQS
Δt
Pin
DQS Logic
Blocks
DLL
DLL
Reference
Clock
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CV-52006
2014.01.10