Watchdog Timer Address Map And Register Definitions; Document Revision History - Altera Cyclone V Device Handbook

24-6

Watchdog Timer Address Map and Register Definitions

reads the wdt_eoi register, or writes 0x76 to the wdt_crr register, the state changes from Decrement
Counter to Load Counter with Restart Timeout Value. In this state, the watchdog counter gets reloaded with
the restart timeout value, and then the state changes back to the first Decrement Counter state. If the counter
again reaches zero, the state changes to Assert System Reset Request. In response, the reset manager resets
the watchdog timer, and gives software the opportunity to reinitialize the timer.
Watchdog Timer Address Map and Register Definitions
The address map and register definitions reside in the hps.html file that accompanies this handbook volume.
Click the link below to open the file.
To view the module description and base address, scroll to and click the link for either of the following
module instances:
• l4wd0
• l4wd1
To then view the register and field descriptions, scroll to and click the register names. The register addresses
are offsets relative to the base address of each module instance.
Related Information
• Introduction to Cyclone V Hard Processor System (HPS)
For more information, refer to the Introduction to the Hard Processor System.
• hps.html
For more information, refer to hps.html.

Document Revision History

Table 24-1: Document Revision History
Date
December 2013
November 2012
May 2012
January 2012
Altera Corporation
Version
2013.12.30
1.2
1.1
1.0
on page 1-1
Changes
Minor formatting updates
Minor updates.
Added programming model and
address map and register
definitions sections.
Initial release.
cv_54024
2013.12.30
Watchdog Timer
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