Altera Cyclone V Device Handbook page 280

10-6
Power-On Reset Circuitry
Figure 10-4: Relationship Between t
The Cyclone V POR circuitry uses an individual detecting circuitry to monitor each of the
configuration-related power supplies independently. The main POR circuitry is gated by the outputs of all
the individual detectors. The main POR signal is asserted when the power starts to ramp up. This signal is
released after the last ramp-up power reaches the POR trip level during power up.
In user mode, the main POR signal is asserted when any of the monitored power goes below its POR trip
level. Asserting the POR signal forces the device into the reset state.
The POR circuitry checks the functionality of the I/O level shifters powered by the V
power supplies during power-up mode. The main POR circuitry waits for all the individual POR circuitries
to release the POR signal before allowing the control block to start programming the device.
Figure 10-5: Simplified POR Diagram for Cyclone V Devices
V
CC
V
CC_AUX
V
CCPD
V
CCPGM
Altera Corporation
and POR Delay
RAMP
Volts
POR trip level
first power
V POR
CC
V POR
CC_AUX
supply
last power
supply
POR delay
t
RAMP
Main POR
Time
configuration
time
and V
CCPD
Modular
Main POR
Power Management in Cyclone V Devices
Send Feedback
CV-52010
2014.01.10
CCPGM