Altera Cyclone V Device Handbook page 535

5-4
FPGA-to-HPS Access to ACP
Bridge Property
Total acceptance
The FPGA-to-HPS bridge contains a GPV, described in The Global Programmers View. The GPV registers
provide settings that adjust the bridge slave properties when the FPGA slave interface is configured to be 32
or 128 bits wide. The slave issuing capability can be adjusted, through the fn_mod register, to allow one or
multiple transactions to be outstanding in the HPS. The slave bypass merge feature can also be enabled,
through the bypass_merge bit in the fn_mod2 register. This feature ensures that the upsizing and
downsizing logic does not alter any transactions when the FPGA slave interface is configured to be 32 or
128 bits wide.
Note: It is critical to provide the correct l4_mp_clk clock to support access to the GPV, as described in
GPV Clocks.
Related Information
• The Global Programmers View
• GPV Clocks
FPGA-to-HPS Access to ACP
When the error correction code (ECC) option is enabled in the level 2 (L2) cache controller, all accesses
from the FPGA-to-HPS bridge to the ACP must be 64 bits wide and aligned on 8-byte boundaries after up-
or downsizing takes place.
Table 5-3: FPGA Master and FPGA-to-HPS Bridge Configurations
The following table lists some possible master and FPGA-to-HPS bridge slave configurations that support accesses
to the L2 cache with ECC enabled.
Soft Logic Master
Width
32 bits
64 bits
128 bits
32 bits
64 bits
128 bits
32 bits
64 bits
128 bits
Altera Corporation
FPGA Slave Interface
32 transactions
on page 5-3
on page 5-14
Soft Logic Master Soft Logic Master Burst
Alignment
8 bytes 4 bytes
8 bytes 8 bytes
8 or 16 bytes 8 or 16 bytes
8 bytes 4 bytes
8 bytes 8 bytes
8 or 16 bytes 8 or 16 bytes
8 bytes 4 bytes
8 bytes 8 bytes
8 or 16 bytes 8 or 16 bytes
Soft Logic Master Burst
Size (Width)
2, 4, 6, 8, 10, 12, 14, or
16 beats
1 to 16 beats
1 to 16 beats
2, 4, 6, 8, 10, 12, 14, or
16 beats
1 to 16 beats
1 to 16 beats
2, 4, 6, 8, 10, 12, 14, or
16 beats
1 to 16 beats
1 to 16 beats
L3 Master Interface
32 transactions
FPGA-to-HPS Bridge
Length Slave Width
32 bits
32 bits
32 bits
64 bits
64 bits
64 bits
128 bits
128 bits
128 bits
HPS-FPGA AXI Bridges
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cv_54005
2013.12.30