Differential Receiver In Cyclone V Devices; Receiver Blocks In Cyclone V Devices - Altera Cyclone V Device Handbook

CV-52005
2014.01.10
Figure 5-37: Serializer Bypass
This figure shows the serializer bypass path. In DDR mode,
mode, data is passed directly through the IOE. In SDR and DDR modes, the data width to the IOE is 1 and
2 bits, respectively.

Differential Receiver in Cyclone V Devices

The receiver has a differential buffer and fractional PLLs that you can share among the transmitter and
receiver, a data realignment block, and a deserializer. The differential buffer can receive LVDS, mini-LVDS,
and RSDS signal levels. You can statically set the I/O standard of the receiver pins to LVDS, SLVS, mini-
LVDS, or RSDS in the Quartus II software Assignment Editor.
Note: To drive the LVDS channels, you must use the PLLs in integer PLL mode.
Related Information
Guideline: Use PLLs in Integer PLL Mode for LVDS

Receiver Blocks in Cyclone V Devices

The Cyclone V differential receiver has the following hardware blocks:
Data realignment block (bit slip)
Deserializer
The following figure shows the hardware blocks of the receiver. In SDR and DDR modes, the data width
from the IOE is 1 and 2 bits, respectively. The deserializer includes shift registers and parallel load registers,
and sends a maximum of 10 bits to the internal logic.
I/O Features in Cyclone V Devices
Send Feedback
FPGA
Serializer
Fabric
2
tx_in
DIN DOUT
tx_coreclock
(LVDS_LOAD_EN, diffioclk, tx_coreclock)
3
Fractional PLL
Differential Receiver in Cyclone V Devices
tx_inclock
2
IOE
IOE supports SDR, DDR, or non-registered datapath
LVDS Transmitter
Note: Disabled blocks and signals are grayed out
on page 5-12
clocks the IOE register. In SDR
tx_out
+
–
Altera Corporation
5-65