Altera Cyclone V Device Handbook page 934

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2013.12.30
Figure 19-5: SPI Slave
Slave SPI and SSP Serial Transfers †
"Motorola SPI Protocol" and the "Texas Instruments Synchronous Serial Protocol (SSP)" contain a
description of the SPI and SSP serial protocols, respectively. †
If the SPI slave is receive only (TMOD=2), the transmit FIFO buffer need not contain valid data because the
data currently in the transmit shift register is resent each time the slave device is selected. The TXE error
flag in the status register (SR) is not set when TMOD=2. You should mask the Transmit FIFO Empty
Interrupt when this mode is used. †
If the SPI slave transmits data to the master, you must ensure that data exists in the transmit FIFO buffer
before a transfer is initiated by the serial-master device. If the master initiates a transfer to the SPI slave when
no data exists in the transmit FIFO buffer, an error flag (TXE) is set in the SPI status register, and the
previously transmitted data frame is resent on txd. For continuous data transfers, you must ensure that the
transmit FIFO buffer does not become empty before all the data have been transmitted. The transmit FIFO
threshold level register (TXFTLR) can be used to early interrupt (Transmit FIFO Empty Interrupt) the
processor, indicating that the transmit FIFO buffer is nearly empty. When a DMA Controller is used, the
DMA transmit data level register (DMATDLR) can be used to early request the DMA Controller, indicating
that the transmit FIFO buffer is nearly empty. The FIFO buffer can then be refilled with data to continue
the serial transfer. †
The receive FIFO buffer should be read each time the receive FIFO buffer generates a FIFO full interrupt
request to prevent an overflow. The receive FIFO threshold level register (RXFTLR) can be used to give early
indication that the receive FIFO buffer is nearly full. When a DMA Controller is used, the DMA receive data
level register (DMARDLR) can be used to early request the DMA controller, indicating that the receive FIFO
buffer is nearly full. †
Related Information
• Motorola SPI Protocol
SPI Controller
Send Feedback
Master Device
DO
DI
SCLK
SS_O
SS_X
on page 19-12
Slave SPI and SSP Serial Transfers †
HPS
SPI Slave
rxd
txd
ss_oe_n
sclk_in
ss_in_n
DI
DO
SCLK
SS
Slave
Peripheral n
19-11
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