Ram Blocks Operations; Memory Blocks Packed Mode Support; Memory Blocks Address Clock Enable Support - Altera Cyclone V Device Handbook

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RAM Blocks Operations

Figure 2-6: Byte Enable Functional Waveform

This figure shows how the

M10K blocks, the write-masked data byte output appears as a "don't care" value because the "current data"

value is not supported.

contents at a0

contents at a1

contents at a2

contents at a3

contents at a4

don't care: q (asynch)

current data: q (asynch)

The M10K memory blocks support packed mode.

The packed mode feature packs two independent single-port RAM blocks into one memory block. The

Quartus II software automatically implements packed mode where appropriate by placing the physical RAM

block in true dual-port mode and using the MSB of the address to distinguish between the two logical RAM

blocks. The size of each independent single-port RAM must not exceed half of the target block size.

The embedded memory blocks support address clock enable, which holds the previous address value for as

long as the signal is enabled (

mode, each port has its own independent address clock enable. The default value for the address clock enable

signal is low (disabled).

Embedded Memory Blocks in Cyclone V Devices

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addressstall = 1

signals control the operations of the RAM blocks. For the

). When the memory blocks are configured in dual-port

RAM Blocks Operations

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