Altera Cyclone V Device Handbook page 798

16-2
Features of the DMA Controller
The DMAC supports the following interface protocols:
• Synopsys protocol
• Serial peripheral interface (SPI)
• Universal asynchronous receiver/transmitter (UART)
• Inter-integrated circuit (I
• FPGA
• ARM protocol
• Quad SPI flash controller
• System trace macrocell (STM
Dual slave interfaces enable the operation of the DMA controller to be partitioned into the Secure state and
Non-secure state. The network interconnect must be configured to ensure that only secure transactions can
access the secure interface. The slave interfaces can access status registers and also directly execute instructions
in the DMA controller.
The DMAC has the following features:
• A small instruction set that provides a flexible method of specifying the DMA operations. This architecture
provides greater flexibility than the fixed capabilities of a Linked-List Item (LLI) based DMA controller.
• Supports multiple transfer types:
• Memory-to-memory
• Memory-to-peripheral
• Peripheral-to-memory
• Scatter-gather
• Supports up to eight DMA channels.
• Supports up to eight outstanding AXI read and eight outstanding AXI write transactions.
• Enables software to schedule up to 16 outstanding read and 16 outstanding write instructions.
• Supports 11 interrupt lines into the MPU subsystem:
• 1 for DMA thread abort
• 8 for events
• 2 for MFIFO buffer ECC
• Single and double bit ECC support
• Supports 31 peripheral request interfaces:
• 8 for FPGA
2
• 8 for I C
• 8 for SPI
• 2 for quad SPI
• 1 for System Trace Macrocell
• 4 for UART
Altera Corporation
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2013.12.30
DMA Controller
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