Altera Cyclone V Device Handbook page 887

17-38
Transmit Descriptor
Figure 17-12: Transmit Descriptor Fetch (Read) Format
31 30
O
TDES0 W
N
Ctrl
TDES1
[31:29]
T D E 2 S
T D E 3 S
Table 17-8: Transmit Descriptor Word 0 (TDES0)
Bit
31 OWN: Own Bit
When set, this bit indicates that the descriptor is owned by the DMA. When this bit is reset,
it indicates that the descriptor is owned by the Host. The DMA clears this bit either when
it completes the frame transmission or when the buffers allocated in the descriptor are read
completely. The ownership bit of the frame's first descriptor must be set after all subsequent
descriptors belonging to the same frame have been set. This avoids a possible race condition
between fetching a descriptor and the driver setting an ownership bit.
30 IC: Interrupt on Completion
When set, this bit sets the Transmit Interrupt (Register 5[0]) after the present frame has
been transmitted.
29 LS: Last Segment
When set, this bit indicates that the buffer contains the last segment of the frame. When
this bit is set, the TBS1 or TBS2 field in TDES1 should have a non-zero value.
28 FS: First Segment
When set, this bit indicates that the buffer contains the first segment of a frame.
27 DC: Disable CRC
When this bit is set, the MAC does not append a CRC to the end of the transmitted frame.
This is valid only when the first segment (TDES0[28]) is set.
26 DP: Disable Pad
When set, the MAC does not automatically add padding to a frame shorter than 64 bytes.
When this bit is reset, the DMA automatically adds padding and CRC to a frame shorter
than 64 bytes, and the CRC field is added despite the state of the DC (TDES0[27]) bit. This
is valid only when the first segment (TDES0[28]) is set.
Altera Corporation
29 28 27 26 25 24 23 22 21
T
T
Ctrl [30:26] Ctrl [24:18]
S
E
Buffer 2 Byte Count [28:16]
u B e f f 2 r
†
20 19 18 17 16 15 14 13 12
Reserved for Status [17:7]
RES
u B e f f 1 r d A r d s e [ s 1 3 ] 0 :
d A r d s e [ s 1 3 ] 0 : r o e N t x e D c s p i r r o t d A
Description
11 10 9 8 7 6 5 4 3
SLOT
Number [6:3]
Buffer 1 Byte Count [12:0]
r d s e [ s 1 3 ] 0 :
†
†
†
Ethernet Media Access Controller
cv_54017
2013.12.30
2 1 0
Reserved
for
Status
[2:0]
†
†
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