Document Revision History - Altera Cyclone V Device Handbook

CV-52006
2014.01.10

Document Revision History

Date
January 2014
External Memory Interfaces in Cyclone V Devices
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Version
2014.01.10 Added Cyclone V SE DLL reference clock input information.
Added the DQ/DQS groups table for Cyclone V SE.
Added the DQS pins and DLLs figure for Cyclone V SE.
Added the PHYCLK networks figure for Cyclone V SE.
Updated the DQ/DQS numbers for the M383 package of Cyclone V E,
GX, and GT variants.
Removed the statement about the bottom hard memory controller
restrictions in the figure that shows the Cyclone V GX C5 hard memory
controller bonding.
Added information about the hard memory controller interface widths
for the Cyclone V SE.
Added the HPS hard memory controller widths for Cyclone V SE, SX,
and ST.
Added related information link to
Guide
Changed all "SoC FPGA" to "SoC".
Added links to Altera's
topics listing the external memory interface performance.
Updated the topic about using DQ/DQS pins to specify that only some
specific DQ pins can also be used as RZQ pins.
Updated the topic about DQS delay chain to remove statements about
using
delayctrlin[6..0]
gray-coded 7 bit settings. This mode is not recommended with the
UniPHY controllers.
Updated topic about hard memory controller bonding support to specify
that bonding is supported only for hard memory controllers configured
with one port.
Changes
for more information about using the delay chains.
External Memory Spec Estimator
signals in UniPHY IP to input your own
Document Revision History
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