Altera Cyclone V Device Handbook page 360

2-22
Quartus II-Software Selected Transmitter Datapath Interface Clock
Related Information
• Transceiver Custom Configurations in Cyclone V Devices
• Transceiver Protocol Configurations in Cyclone V Devices
Quartus II-Software Selected Transmitter Datapath Interface Clock
The Quartus II software automatically selects the appropriate clock from the FPGA fabric to clock the
transmitter datapath interface.
The following figure shows the transmitter datapath interface of two transceiver non-bonded channels
clocked by their respective transmitter PCS clocks, which are forwarded to the FPGA fabric.
Figure 2-17: Transmitter Datapath Interface Clocking for Non-Bonded Channels
Channel 1
Channel 0
The following figure shows the transmitter datapath interface of three bonded channels clocked by the
tx_clkout[0] clock. The tx_clkout[0] clock is derived from the central clock divider of channel 1
or 4 of the two transceiver banks.
Altera Corporation
TX
Phase
Transmitter Data
Compensation
FIFO
tx_clkout[1]
Parallel Clock
TX
Phase
Transmitter Data
Compensation
FIFO
tx_clkout[0]
Parallel Clock
FPGA Fabric
Transmitter Data
tx_coreclkin[1]
Transmitter Data
tx_coreclkin[0]
Transceiver Clocking in Cyclone V Devices
Channel 1 Transmitter
Data and Control Logic
Channel 0 Transmitter
Data and Control Logic
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CV-53002
2013.05.06