Altera Cyclone V Device Handbook page 482

2-8
Main Clock Group
Table 2-3: Main Clock Group Clocks
System Clock Name
mpu_clk
mpu_l2_ram_clk
mpu_periph_clk
l3_main_clk
l3_mp_clk
l3_sp_clk
l4_main_clk
l4_mp_clk
l4_sp_clk
dbg_at_clk
dbg_trace_clk
dbg_timer_clk
dbg_clk
main_qspi_clk
Altera Corporation
Freq
uency
Main PLL C0
mpu_clk/2
mpu_clk/4
Main PLL C1
l3_main_clk or l3_main_clk/
2
l3_mp_clk or l3_mp_clk/2
Main PLL C1
osc1_clk/16 to 100 MHz divided
from main PLL C1 or peripheral PLL
C4
osc1_clk/16 to 100 MHz divided
from main PLL C1 or peripheral PLL
C4
osc1_clk/4 to main PLL C2/2
osc1_clk/16 to main PLL C2
osc1_clk to main PLL C2
dbg_at_clk/2 or dbg_at_clk/
4
Main PLL C3
Main PLL C4
Constraints and Notes
Clock for MPU subsystem,
including CPU0 and CPU1
Clock for MPU level 2 (L2) RAM
Clock for MPU snoop control unit
(SCU) peripherals
, such as the general interrupt
controller (GIC)
Clock for L3 main
switch
Clock for L3 master peripherals
(MP) switch
Clock for L3 slave peripherals (SP)
switch
Clock for L4 main bus
Clock for L4 MP bus
Clock for L4 SP bus
™
Clock for CoreSight
debug trace bus
™
Clock for CoreSight
debug Trace Port Interface Unit
(TPIU)
Clock for the trace timestamp
generator
Clock for Debug Access Port
(DAP) and debug peripheral bus
Quad SPI flash internal logic clock
Clock Manager
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2013.12.30