Altera Cyclone V Device Handbook page 699

cv_54011
2013.12.30
If the bytcnt is zero (the block size must be greater than zero) the transfer is an open-ended block transfer.
The data transmit state machine for this type of data transfer continues the block-write data transfer until
the host software issues an SD/SDIO STOP or STOP_TRANSMISSION (CMD12) command.
Data Receive
The data-receive state machine receives data two clock cycles after the end bit of a data read command, even
if the command path detects a response error or response CRC error. If a response is not received from the
card because a response timeout occurs, the BIU does not receive a signal that the data transfer is complete.
This happens if the command sent by the controller is an illegal operation for the card, which keeps the card
from starting a read data transfer.
If data is not received before the data timeout, the data path signals a data timeout to the BIU and an end to
the data transfer done. Based on the value of the transfer_mode bit in the cmd register, the data-receive
state machine gets data from the card data bus in a stream or block(s).
Figure 11-9: Data Receive State Machine
Stream Data Read
A stream-read data transfer occurs if the transfer_mode bit in the cmd register is set to 1, at which time
the data path receives data from the card and writes it to the FIFO buffer. If the FIFO buffer becomes full,
the card clock stops and restarts once the FIFO buffer is no longer full.
An open-ended stream-read data transfer occurs if the bytcnt register is set to 0. During this type of data
transfer, the data path continuously receives data in a stream until the host software issues an SD/SDIO
STOP command. A stream data transfer terminates two clock cycles after the end bit of the STOP command.
If the bytcnt register contains a nonzero value and the send_auto_stop bit in the cmd register is set
to 1, a STOP command is internally generated and loaded into the command path, where the end bit of the
STOP command occurs after the last byte of the stream data transfer is received. This data transfer can
terminate if the host issues an SD/SDIO STOP or STOP_TRANSMISSION (CMD12) command before all
the data bytes are received from the card.
Single-block Data Read
If the ctype register is set to a 1-bit, 4-bit, or 8-bit data transfer, data is received from 1, 4, or 8 data lines,
respectively, and CRC-16 is separately generated and checked for 1, 4, or 8 data lines, respectively. If there
is a CRC-16 mismatch, the data path signals a data CRC error to the BIU. If the received end bit is not 1, the
BIU receives an End-bit Error (EBE).
SD/MMC Controller
Send Feedback
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†
load_new_cmd,
data_expected, Read
Data & Block Transfer Data Rx
Idle
Stop Data Command
Rx
Data Block
Byte Count
Remaining != 0
Read
Wait
Block Done
†
†
†
Stop Data Command
load_new_command,
data_expected, Read
Data & Stream Transfer
Rx
Data Stream
Byte Count
Remaining = 0
or Stop Data Command
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11-21
Data Receive
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