Receiver Pma Datapath - Altera Cyclone V Device Handbook

CV-53001
2013.05.06
data eye opening at the far-end receiver. The pre-emphasis circuitry provides first post-tap settings with up
to 6 dB of high-frequency boost.
Programmable Transmitter V
The transmitter buffers have on-chip biasing circuitry to establish the required V
The circuitry supports a V
Note: On-chip biasing circuitry is available only if you select one of the Termination logic options in order
to configure OCT. If you select external termination, you must implement off-chip biasing circuitry
to establish the V
Programmable Transmitter Differential OCT
The transmitter buffers support optional differential OCT resistances of 85, 100, 120, and 150 Ω . The
resistance is adjusted by the on-chip calibration circuit during calibration, which compensates for PVT
changes. The transmitter buffers are current mode drivers. Therefore, the resultant V
transmitter termination value.
Transmitter Protocol Specific
There are two PCIe features in the transmitter PMA section—receiver detect and electrical idle.
• PCIe Receiver Detect—The transmitter buffers have a built-in receiver detection circuit for use in PCIe
configurations for Gen1 and Gen2 data rates. This circuit detects whether there is a receiver downstream
by sending out a pulse on the common mode of the transmitter and monitoring the reflection.
• PCIe Electrical Idle—The transmitter output buffers support transmission of PCIe electrical idle (or
individual transmitter tri-state).
Related Information
Altera Transceiver PHY IP Core User Guide

Receiver PMA Datapath

There are three blocks in the receiver PMA datapath—the receiver buffer, channel PLL configured for clock
data recovery (CDR) operation, and deserializer.
Table 1-6: Functional Blocks in the Receiver PMA Datapath
Block
Receiver Buffer
Transceiver Architecture in Cyclone V Devices
Send Feedback
CM
setting of 0.65 V.
CM
at the transmitter output buffer.
CM
• Receives the serial data stream and feeds the stream to the channel PLL
if you configure the channel PLL as a CDR
• Supports the following features:
• Programmable CTLE (Continuous Time Linear Equalization)
• Programmable DC gain
• Programmable V
• On-chip biasing for common-mode voltage (RX V
• I/O standard (1.5 V PCML, 2.5 V PCML, LVDS, LVPECL )
• Differential OCT (85, 100, 120 and 150 Ω )
• Signal detect
Programmable Transmitter V
Functionality
current strength
CM
1-15
CM
at the transmitter output.
CM
is a function of the
OD
)
CM
Altera Corporation