Interface Signals - Altera Cyclone V Device Handbook

cv_54012
2013.12.30
RX FIFO not empty
RX FIFO full
Indirect read partition overflow

Interface Signals

The quad SPI controller provides four chip select outputs to allow control of up to four external quad SPI
flash devices. The outputs serve different purposes depending on whether the device is used in single, dual,
or quad operation mode. Table 12–3 lists the I/O pin use of the quad SPI controller interface signals for each
operation mode.
Table 12-4: Interface Signals
Signal
data[0]
data[1]
data[2]
data[3]
ss_n[0]
ss_n[1]
ss_n[2]
ss_n[3]
sclk
Quad SPI Flash Controller
Send Feedback
Interrupt Source
Mode
Single
Dual or quad
Single
Dual or quad
Single or dual
Quad
Single, dual, or quad
Single, dual, or quad
Description
This condition occurs only in legacy SPI mode. When
0, the RX FIFO buffer is empty. When 1, the RX FIFO
buffer is not empty.
This condition occurs only in legacy SPI mode. When
0, the RX FIFO buffer is not full. When 1, the RX FIFO
buffer is full.
Indirect Read Partition of SRAM is full and unable to
immediately complete indirect operation
Direction
Output
Bidirectional
Input
Bidirectional
Output
Bidirectional
Bidirectional
Output
12-13
Interface Signals
Function
Data output 0
Data I/O 0
Data input 0
Data I/O 1
Active low write protect
Data I/O 2
Data I/O 3
Active low slave select 0
Active low slave select 1
Active low slave select 2
Active low slave select 3
Serial clock
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