Altera Cyclone V Device Handbook page 894

cv_54017
2013.12.30
Bit
10
9
8
7
6
5
4
3
Ethernet Media Access Controller
Send Feedback
VLAN: VLAN Tag
When set, this bit indicates that the frame to which this descriptor is pointing is a VLAN
frame tagged by the MAC. The VLAN tagging depends on checking the VLAN fields of
received frame based on the Register 7 (VLAN Tag Register) setting.
FS: First Descriptor
When set, this bit indicates that this descriptor contains the first buffer of the frame. If the
size of the first buffer is 0, the second buffer contains the beginning of the frame. If the size
of the second buffer is also 0, the next descriptor contains the beginning of the frame.
LS: Last Descriptor
When set, this bit indicates that the buffers pointed to by this descriptor are the last buffers
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of the frame
Timestamp Available, IP Checksum Error (Type1), or Giant Frame
When advanced timestamp feature is present, when set, this bit indicates that a snapshot
of the Timestamp is written in descriptor words 6 (RDES6) and 7 (RDES7). This is valid
only when the Last Descriptor bit (RDES0[8]) is set.
When IP Checksum Engine (Type 1) is selected, this bit, when set, indicates that the 16-bit
IPv4 Header checksum calculated by the EMAC did not match the received checksum bytes.
Otherwise, this bit, when set, indicates the Giant frame Status. Giant frames are larger than
1,518-byte (or 1,522-byte for VLAN or 2,000-byte when Bit 27 (2KPE) of MAC Configuration
register is set) normal frames and larger than 9,018-byte (9,022-byte for VLAN) frame when
Jumbo frame processing is enabled.
LC: Late Collision
When set, this bit indicates that a late collision has occurred while receiving the frame in
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the half-duplex mode.
FT: Frame Type
When set, this bit indicates that the receive frame is an Ethernet-type frame (the LT field
is greater than or equal to 0x0600). When this bit is reset, it indicates that the received frame
is an IEEE802.3 frame. This bit is not valid for Runt frames less than 14 bytes.
RWT: Receive Watchdog Timeout
When set, this bit indicates that the receive Watchdog Timer has expired while receiving
the current frame and the current frame is truncated after the Watchdog Timeout.
RE: Receive Error
When set, this bit indicates that the gmii_rxer_i signal is asserted while gmii_rxdv_
i is asserted during frame reception.
Receive Descriptor Field 0 (RDES0)
Description
17-45
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