Altera Cyclone V Device Handbook page 111

5-14
Guideline: Using LVDS Differential Channels
Note: The figures in this section show guidelines for using corner PLLs but do not necessarily represent
the exact locations of the high-speed LVDS I/O banks.
Figure 5-2: Corner PLLs Driving LVDS Differential I/Os in the Same Bank
Figure 5-3: Invalid Placement of Differential I/Os Due to Interleaving of Channels Driven by the Corner PLLs
Related Information
Clock Networks and PLLs in Cyclone V Devices
Altera Corporation
Corner PLL
Reference CLK
Diff RX Diff TX
Diff RX Diff TX
Diff RX Diff TX
Diff RX Diff TX
Diff RX Diff TX
Diff RX Diff TX
Diff RX Diff TX
Diff RX Diff TX
Diff RX Diff TX
Diff RX Diff TX
Reference CLK
Corner PLL
Corner PLL
Reference CLK
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Reference CLK
Corner PLL
Corner PLL
Reference CLK
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Reference CLK
Corner PLL
on page 4-1
Channels Driven
by Corner PLL
No Separation
Buffer Needed
Channels Driven
by Corner PLL
I/O Features in Cyclone V Devices
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CV-52005
2014.01.10