Altera Cyclone V Device Handbook page 621

cv_54008
2013.12.30
Name
Write Address Channel Signals
AWID
AWADDR
AWLEN
AWSIZE
AWBURST
AWREADY
AWVALID
Write Data Channel Signals
WID
WDATA
WSTRB
WLAST
WVALID
WREADY
SDRAM Controller Subsystem
Send Feedback
Bits
4
32
4
3
2
1
1
4
32, 64, 128 or 256
4, 8, 16, 32
1
1
1
Direction
In Write identification tag
In Write address
In Write burst length
In Width of the transfer size
In Burst type
Out Indicates ready for a write command
In Indicates valid write command.
In Write data transfer ID
In Write data
In Byte-based write data strobe. Each bit width
corresponds to 8 bit wide transfer for 32-bit
wide to 256-bit wide transfer.
In Last transfer in a burst
In Indicates write data+strobes are valid
Out Indicates ready for write data and strobes
8-21
AXI Port
Function
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