Master Spi And Ssp Serial Transfers - Altera Cyclone V Device Handbook

19-18

Master SPI and SSP Serial Transfers

Master SPI and SSP Serial Transfers
Figure 19-11: Master SPI or SSP Serial Transfer Software Flow
To complete an SPI or SSP serial transfer from the SPI master, follow these steps:
1. If the SPI master is enabled, disable it by writing 0 to the SSI Enable register (SSIENR).
2. Set up the SPI master control registers for the transfer; you can set these transfers in any order.
Altera Corporation
Idle
Disable SPI
Configure Slave by Writing
CTRLR0, CTRLR1, TXFTLR,
RXFTLR, MWCR, & IMR
Enable SPI
Write Data
to Tx FIFO
TMOD = 10
Wait for Master
to Select Slave
Transfer
in Progress
yes
Interrupt Service
Interrupt?
If the transmit FIFO makes the request
no
and all data has not been sent, write
data to the transmit FIFO.
If the receive FIFO makes the request,
read data from the receive FIFO.
Busy?
yes
no
Read Rx
FIFO
Routine
TMOD = 01
cv_54019
2013.12.30
SPI Controller
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