Transceiver Architecture In Cyclone V Devices - Altera Cyclone V Device Handbook

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Describes the Cyclone

and receiver channel datapaths.

28-nm Cyclone V devices provide transceivers with the lowest power requirement at 3.125 and 6.144

Gigabits per second (Gbps). These transceivers comply with a wide range of protocols and data rate standards;

however, 6.144 Gbps support is limited to the common public radio interface (CPRI) protocol only.

Cyclone V devices have up to 12 transceiver channels with serial data rates between 614 megabits per second

(Mbps) and 6.144 Gbps and have backplane-capable transceiver support for PCI Express

Specification 2.0 Gen1 and Gen2 up to x4 bonded channels.

Cyclone V transceiver channels are full-duplex and clock data recovery (CDR) based with physical coding

sublayer (PCS) and physical medium attachment (PMA) layers.

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Transceiver Architecture in Cyclone V Devices

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V transceiver architecture, clocking, channels, channel bonding, and transmitter

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